1. Technical Field
The present invention relates generally to Integrated Circuit (IC) memory devices and more specifically to burn-in stress testing of synchronous IC memory devices.
2. Discussion of the Prior Art
Low power integrated circuit (IC) memory devices possess a time-out feature that enables the device to conserve power. The time-out feature of a static random access memory (SRAM) device, for instance, may conserve power by turning off all wordlines of a memory cell after a given period of time. For a 1 Meg SRAM device the time-out feature may cause the wordlines of the memory cell to be turned off after approximately 40 nS to 50 nS.
While this time-out feature conserves power and thus makes the device a low power device, devices having this time-out feature are difficult to stress test in a burn-in oven since the wordlines must be on in order to stress the memory cells of the device. The devices cycle at no faster than several microseconds. Thus, for the majority of the time of a given memory cycle, such as all but 40 nS to 50 nS in our example, the wordlines are off and the memory cells are not being stressed at all. In order to compensate for this small window of opportunity during which memory cells of the device may be stress tested, the device must be put through many cycles while in the burn-in oven. Increasing the time required in the burn-in oven of course increases the cost of stress testing a device.
There is thus an unmet need in the art to be able to disable a time-out feature of an IC memory device during a stress test mode of the device in order that stress testing of the device in a burn-in oven may be accomplished in a timely and economical manner. It is desirable that any solution that allows for the time-out feature of an IC memory device to be disable be compatible with the existing pin-out of the IC memory device.
It is an object of the invention to disable a time-out feature of an IC memory device during a stress test mode of the device in order that stress testing of the device in a burn-in oven may be accomplished in a timely and economical manner.
It is further an object of the invention to disable the time-out feature of an IC memory device during a stress test mode of the device by leaving on the wordlines of the device for the duration of the memory cycle for maximum burn-in-efficiency.
It is yet another object of the invention to disable the time-out feature of an IC memory device during a stress test mode of the device using the existing pin-out of the IC memory device.
In accordance with the present invention, an integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure employed is a burn-in stress test mode circuit of an integrated circuit device.
The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level. The supply voltage and/or temperature are monitored and when the supply voltage and/or temperature exceeds the predetermined level, entry into a burn-in mode of the integrated circuit device that disables the time-out feature of the integrated circuit device is affected. A device flag or a device pin of the integrated circuit device may be monitored to determine when the integrated circuit device is in the burn-in mode.